Inductor Saturation Tester

As a result of recent work on switchmode power converters I needed the ability to measure the saturation properties of inductors. This simple instrument was built to allow visualisation of the current ramp as an inductor charges from a constant voltage, the current vrs time gradient being an indication of inductance (as the current through a perfect inductor rises linearly with time when charged from a constant voltage). When an inductor's magnetic material saturates the inductor suffers a drop in inductance; essentially the matter in the core can no longer contribute to the magnetisation, only the vacuum in the field remains capable of further magnetisation. This rapid loss of inductance is visible as a steepening knee in the current curve; the instantaneous inductance drops and current rises more rapidly with time.

The Testing Scheme

Inductor Test Scheme Diagram

The testing scheme is simple, and as such suffers from some limitations. The Ron of the MOSFET changes with current somewhat, and along with the RShunt resistance (used to measure the inductor current) limits the maximum current the tester can deliver. These resistances along with the inductor parasitic resistance also drop the charging voltage as current increases effecting linearity and ease of direct-reading. The supply and capacitor must provide the current demands as the inductor charges, their ESR and capacity is important to ensure the voltage doesn't sag too significantly. Simple as the testing scheme may be it is capable of fair accuracy with careful use and is very usable for relative measurements.

An Implementation

The switching circuit itself presents no problems, a MOSFET with a low Ron value and reasonable drain current limit is selected. I used an MTP3055 because it was the best device I had available, there are better devices for this service. The Vds breakdown is not especially critical in this application as the commutation diode prevents large voltages from being induced across the coil. There will of course be some spikes from the stray inductances, but it will have very little energy and the large MOSFETs used will absorb any left without damage. The diode must be rated for the discharge current and ideally be as fast as possible to allow visualisation close to the switching transient. Its forward voltage constrains the pulse repetition frequency as the discharge time is inversely proportional to the voltage the inductor is discharged at, the pulse duty-cycle must be less than Vdiode/Vsupply.

The MOSFET gating pulse source needs to saturate the MOSFET as rapidly as possible and keep the gate high as the source rises (with the drop across the shunt resistance. Most larger power MOSFETs like to be driven to 12 volts rather than the 5 volts normally used for "logic compatible" devices. To control the pulsing I decided to use a Atmel ATtiny13V microcontroller. It can implement the constant duty cycle, variable "on" time quite simply compared to discrete circuits. The tiny13 has its own 5 Volt supply rail. A fairly fast buffering circuit shifts the tiny13 logic level up to the main supply rail to ensure good MOSFET gate drive. The risetime of the gate voltage is better than 1 us and is a bit of a compromise to limit the power dissipation of the drive circuit - it could be improved but it works well-enough. The buffer also tends to isolate the tiny13 from the higher power side of the circuit, during development I blew up a microcontroller accidentally. I am not completely sure what killed it, it had protection diodes across the output (and likely has them internally as well), but I've included a 5.1 Volt Zener across the output in the final to protect it.

Inductor Tester Circuit Diagram

The control voltage pot and software is set so frequency drops with clock-wise rotation of the switch-pot (which also implements the on-switch). The "minimum" position is the highest frequency (shortest charge time and smallest peak inductor current) which is a sensible basis for beginning measurement of a new inductor. The frequency is then dropped increasing the peak current until either the core saturation is visible or the tester runs into its current limit. The repetition frequency is adjustable from about 8.7 kHz down to 91 Hz or so, giving charge times from 4.6 us to 440 us. This means 2.2 uH inductors can be tested to a 25 Amp limit (and 210 uH the other 25 Amp limit, but larger inductances can be tested to lower currents, 1 mH to 5.3 Amps and 10 mH to 527 mA, etc). The software could be changed to allow longer charge times for testing larger inductances to the full current limit, but in most cases their DC resistance would require more supply voltage to achieve the maximum current. Bear in mind the stored energies and involved with inductors at high currents, 10 mH @ 25 Amps is more than 3 Joules, which while relatively small dumping that in 10 ms is 300 Watts (and a 7.8 kW charge in 400 us which would need a 625 Volt supply capable of more than 15 kW peak).

The storage capacitor must be low ESR and quite large. I used a pair of 2500 uF low ESR capacitors in parallel but still suffer a worst-case 4 volt of droop with the test terminals shorted (the load current peaking at 25 Amps). The supply current is of course smaller as the load is only powered for about 4% of the time, allowing a conventional 1 Amp bench supply to be used. For best accuracy in inductance measurement you should measure the voltage at the inductor terminals during testing and take droop into account. For most inductors these extreme currents will not be required, especially if you are winding your own - you can just add turns to achieve saturation with a lower current. Saturation current measurements are not affected by voltage droop as long as saturation can be achieved with the available current.

Building The Tester

Initial work was done with just the circuit on a solderless breadboard, but I decided to make it a permanent piece of test equipment. The control and switching boards were assembled and jiffy box large enough to hold them used. A pair of banana binding posts allow connection of the inductor under test and are spaced to accept a fixture I used with my LC tester for small devices. (For historic reasons the spacing on the LC tester is metric, not the standard imperial one which would allow mating with BNC to banana plug and other adapters - this was perhaps a bad choice - I was being lazy, avoiding building another IC-socket to banana fixture with the rare and expensive threaded-stud banana plugs.)

Front View of the Inductor Saturation Tester

The connections to the power supply and CRO are made through three RCA sockets. I made up a pair of RCA to BNC leads to interface with the CRO.

The RCA Sockets for Power and CRO Outputs

The Dynamo labelling is pretty rough and ready, perhaps I should have invested the time to design a the labelling on the PC and printed/laminated it. As a piece of test equipment I knocked up for quick investigations into power supply inductors I think it will suffice, it isn't meant to be a polished display piece. Inside is a bit of a mess too, fitting the large storage capacitors meant mounting them on their side.

The Inside of the Inductor Saturation Tester

Using the Tester

The trigger output goes to the CRO trigger input or perhaps the X channel if it is a dual-trace unit. The 100 mV/A output goes to the vertical Y input. The timebase on the CRO is set to deliver a suitable sweep rate and the triggering configured to use the trigger output. The Y sensitivity is adjusted to match the currents expected. Once the inductor is attached the unit is switched on with the switch-pot and the pot advanced until the inductor is saturating. Adjustments of the timebase and sensitivity are needed to localise some features for closer inspection but the procedure is quite simple.

A Typical Inductor Test Trace

The display above is quite typical. The initial linear region shows constant inductance as the current ramps up through the inductor. The knee is where the inductance drops as the core material saturates. The slope becomes steeper because the inductance drops. Towards the end of the sweep the tester is running out of voltage as the current drops larger and large voltages across the resistance in the loop, causing the current increase with time to no longer be linear.

In the limiting cases, an open circuit (or infinite inductance) the trace simply remains at the baseline, no current flows and no voltage is dropped across the shunt. For a short circuit (zero inductance) the current jumps straight up to the limit of the tester (about 25 Amps for this unit). Some sag is visible in such a situation (and often in use far beyond inductor saturation), this is caused by the voltage sagging as the supply capacitor discharges under the heavy current. Inductances between zero and infinity give varying slopes, with steeper slopes for less inductance. Saturation always results in a decrease in inductance and increase in trace slope. Current limiting because of inductor DC resistance is visible as a flattening of the trace and may occur before saturation with a given supply voltage. Some core materials exhibit non-linearity long before true saturation and give a gentle curve before the knee (iron power cores in particular) and in one case with a random powder core from the junkbox I observed non-monotonic inductance changes with current.

Closer Trace Showing Linear and Saturated Regions

For measurement purposes you zoom in on the linear magnetisation region and use as much of the graticule as possible to extract the current/time slope. Inductance is equal to the charging Voltage times the Time delta on the Current delta; L = Vt/I. The Voltage is the least well known parameter and for accuracy you should measure the voltage seen at the inductor directly (use the other CRO channel). The ratio of the slopes (inductances before and after core saturation) gives you an idea of the core relative permeability. The saturation region inductance is essentially the vacuum inductance of the winding.

Note that with small inductances and long charge times the power levels can be quite large. The MOSFET has only a modest heatsink and along with the shunt resistors can get quite hot with extended use. Measurements can generally be made long before you are in danger of damaging the device.

DC Core Bias

As a result of some discussion on the EMRFD mailing list about remanence and this method of saturation assessment I tried biasing the ferrite core of a 1mH choke with a DC field (provided by a small NIB permanent magnet). Here is a video of the shift in saturation point caused by first biasing the core to augment in applied field and then to oppose it. When opposing, the increase in linear region appears to be a bit more than twice the unbiased region when the core is biased such that saturation is visible at both ends. This is perhaps due to the remanence of the material. I'd like to perform a true H-B plot, but that appears to require two windings (of known turns ratio to measure B) and an integrator - something I can't easily do to commercial chokes - but something I will try shortly.

I wonder about biasing the core permanently in service? For unipolar excitation this gives you at least twice the saturation limit. I'm not quite sure what the long-term effect would be on a permanent magnet in this service, my NIB magnet did seem to get warm in my fingers as I held it and NIB has a rather low Curie point. The bias could be achieved with a (high turn-count) DC biasing winding, except for the voltages induced across it. Topologies like a magnetic amplifier come to mind with two cores that allow cancellation of the voltage induced in the bias winding. The "wasted" current in the bias winding might power the control circuit to achieve high efficiency in lower powered circuits. Note also the shift in saturation point could be used for measuring magnetic fields. The fluxgate magnetometer uses this principle, and combined with synchronous detection can be extremely sensitive...



title type size
Inductor Test Scheme Diagram Source application/postscript 12.815 kbytes
Inductor Tester Circuit Diagram Source application/postscript 17.504 kbytes